DVCon
Design and Verification Conference and Exhibition


National trade fair
San Jose, USA

General Overview


Location DoubleTree Hotel
San Jose
USA
America

About the expo
DVCon attendees have the opportunity to take part in the many informal, but often intense, technical discussions that pop-up around the conference venue among 800+ design and verification engineers and engineering managers. This networking opportunity among peers is possibly the greatest benefit to DVCon attendees. Finally, DVCon attendees have access to the vendors of advanced design and verification tools, IP/VIP and services who exhibit at the conference.
More Facts
Show type National trade fair
Branches Electronics, Software
Products / Sectors Hardware design and verification languages. Application of languages, tools and methodologies for the design and verification of electronic systems and integrated circuits. Usage of specialized design and verification languages such as Verilog, SystemVerilog, VHDL, PSL SystemC, e, and VERA, as well as general purpose languages such as C and C++. Tools and methodologies include the use of testbench automation, hardware-assisted verification, hardware / software co-verification, assertion-based and formal verification, and transaction-level system design and verification
Open to Trade visitors
Frequency Annual
Expo Website http://www.dvcon.org

EVENT ORGANISER


MP Associates, Inc.

1721 Boxelder St., Ste. 107
80027 Louisville
USA
America
Phone: +1 303/530-4333
Fax: +1 303/530-4334
Open Website

DVCon
San Jose
California
USA
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